The present invention relates generally to power semiconductor devices, and in particular relates to power MOSFETs.
A fundamental consideration in the design of integrated circuits is the physical size of the electrical components to be included on the integrated circuits. The value of an integrated circuit increases as the size of the electrical components on the integrated circuit decreases, since the number of electrical components that can be included on a given integrated circuit increases as the physical size of the electrical components is reduced.
Integrated circuits often include different types of electrical components, ranging from logic components (e.g., flip-flops) and analog components (e.g., NPN bipolar junction transistors) to power electronics components such as power MOSFETs (metal-oxide-semiconductor field-effect transistors). Although recent improvements in the design of integrated circuits have led to reductions in size for each of these types of electrical components, there has grown a disparity in the rates of size reduction between different types of electrical components. In particular, where in certain instances the sizes of logic components have been reduced by two orders of magnitude, the sizes of power components have only been reduced one or less order of magnitude.
That the rates of size reduction of power components on integrated circuits have been lower than the rates of size reduction for some other integrated circuit components is significant. On many integrated circuits, power components already take up one-third to one-half of the total area of the integrated circuits. As the sizes of other types of electrical components continue to shrink at a faster rate than the sizes of power components, the proportion of the total area of integrated circuits that is taken up by power components continues to increase. Thus, the rates of reduction in the overall sizes of integrated circuits are being increasingly limited by the slow rates of size reduction concerning power components.
A figure of merit that is commonly employed as an indication of the relative sizes of power components on integrated circuits is the specific on-resistance, which is defined as the resistance of the power component when it is conducting current in its on state, multiplied by the area of the power component. Minimization of the specific on-resistance of a power component corresponds to minimization of the area, and consequently the size, of the power component. One type of power component for which reductions in specific on-resistance (and consequently reductions in size) have become increasingly difficult is the lateral DMOSFET, which is a double-diffused metal-oxide-semiconductor field-effect transistor, and which is xe2x80x9clateralxe2x80x9d insofar as the active, conducting portions of the DMOSFET are all located along a top surface of the device.
Reductions in the specific on-resistance of the lateral DMOSFET are difficult largely because it is typically desirable for the DMOSFET to have a high breakdown voltage (BVdss) so that the DMOSFET can sustain high voltages applied between its drain and source terminals in its off state without conducting current. In order to have a high breakdown voltage, a conventional lateral DMOSFET typically requires a long drift region between the source and drain regions of the lateral DMOSFET, which increases the specific on-resistance (and size) of the lateral DMOSFET. Although reduced doping of the drift region also tends to increase the breakdown voltage, such reduced doping of the drift region is counterproductive insofar as it tends to further increase the specific on-resistance. Further, size reductions in the cross sectional width of the drift region (perpendicular to the axis connecting the drain and source terminals) are not effective for reducing the specific on-resistance because, in addition to reducing the area of the drift region, such size reductions also tend to reduce the conductivity and increase the resistance of the drift region when the lateral DMOSFET is in its on state. Increased resistance within the drift region is particularly undesirable because it increases the power consumption and heat dissipation of the lateral DMOSFET when it is operating in its on state.
Referring to FIG. 1 (Prior Art), schematically one embodiment of a conventional NMOS lateral DMOSFET 10 includes a source region 12 that is doped with P+ type impurities, a drift region 14 that is doped with Nxe2x88x92 type impurities, and a drain region 16 that is doped with N+ type impurities. As shown by a first curve 22 in FIG. 2 (Prior Art), when the lateral DMOSFET 10 is in its off state (because the voltage applied between the gate and source of the DMOSFET is zero) and a positive voltage is applied between the drain region 16 and the source region 12, a nonzero electric field is created within the drift region 14. The electric field varies approximately linearly from a maximum occurring at or near a junction 18 between the source region 12 and the drift region 14 and a minimum (e.g., zero electric field) occurring at a point 24 somewhere along the drift region.
The voltage applied to the lateral DMOSFET 10 between the drain region 16 and the source region 12 exceeds the breakdown voltage when the voltage becomes sufficiently large such that the maximum electric field exceeds a critical level, for example, 40 Volts per micron. Consequently, the lateral DMOSFET must be designed so that, given off state voltages between the drain region 16 and the source region 12 that are below the desired breakdown voltage, the maximum electric field does not exceed the critical level. As the length of the drift region 14 decreases, the critical level of the electric field is attained at a lower voltage. As a result, for the lateral DMOSFET to be able to sustain a desired breakdown voltage, the length of the drift region must be maintained above a minimum length. Further, as a result of the need for the drift region length to be maintained above a certain minimum length, the specific on-resistance is compromised, and hence there is a fundamental tradeoff between the specific on-resistance and the breakdown voltage.
It is known in the art to modify the simple NMOS lateral DMOSFET discussed above in several ways so that the specific on-resistance of the DMOSFET can be reduced without compromising the desired high breakdown voltage. One known modification is to provide an additional layer of silicon doped with Pxe2x88x92 type impurities underneath the drift region 14, which is shown in FIG. 1 as a RESURF region 32. Such a modified lateral DMOSFET is termed a NMOS Reduced Surface Field (RESURF) lateral DMOSFET 20. The RESURF lateral DMOSFET 20 can have the same breakdown voltage as, and a lower specific on-resistance than, a simple lateral DMOSFET because extra depletion of electrons occurs from the drift region of the RESURF lateral DMOSFET when the DMOSFET is in its off state. Specifically, extra depletion occurs due to the interaction of the drift region 14 with the RESURF region 32, in addition to the normal depletion that occurs between the drift region and the source region 12.
As shown by curve 28 of FIG. 2, the extra depletion within the RESURF lateral DMOSFET 20 causes the nonzero electric field to be distributed throughout the drift region 14 such that the electric field distribution is flattened and, in particular, reduces the maximum electric field that occurs at any point within the drift region. Specifically, given the application of the same voltage between the drain region 16 and source region 12 of the RESURF lateral DMOSFET 20 as assumed with respect to the simple lateral DMOSFET 10 discussed above (where both DMOSFETs have drift regions of equal dimensions), the resulting electric field within the drift region 14 is lower at the junction 18 for the RESURF lateral DMOSFET than for the simple lateral DMOSFET. With the adding of the RESURF region 32 to the simple lateral DMOSFET to create the RESURF lateral DMOSFET 20, therefore, a greater voltage must be applied between the drain region 16 and source region 12 of the DMOSFET to produce a maximum electric field that exceeds the critical level above which breakdown occurs than for the simple lateral DMOSFET 10. Consequently, a RESURF lateral DMOSFET can have a smaller drift region 14, both in terms of the length of the drift region between the drain region 16 and source region 12 and in terms of the cross sectional width of the drift region, or a higher doping level than a comparable simple lateral DMOSFET having the same breakdown voltage.
A second known modification for reducing the specific on-resistance of a lateral DMOSFET without compromising its breakdown voltage is to divide up the drift region into multiple parallel columns that extend between the source region and the drain region, where the columns alternate between columns doped with Pxe2x88x92 impurities and columns doped with Nxe2x88x92 impurities. Such a modified drift region is termed a superjunction. Referring to FIG. 3 (Prior Art), a RESURF lateral DMOSFET having this modified drift region is termed a RESURF superjunction lateral DMOSFET 30 and includes a drift region or layer 54 positioned above a RESURF region or layer 50, which in turn is positioned above a substrate region 40.
The drift region 54 extends between a drain 56 and a source region 52 of the RESURF superjunction lateral DMOSFET 30. The drain is doped with N+ impurities and the source region 52 includes a base region 62 doped with P+ impurities, a P+ region 64 doped with P+ impurities and a N+ region 66 doped with N+ impurities. The base region 62 surrounds the P+ and N+ regions 64, 66, and the P+ region and N+ region typically are coupled to one another by way of metallization (not shown) along the surface of the DMOSFET 30. The RESURF superjunction lateral DMOSFET 30 further includes a gate 68 along its surface. The base region 62 acts both as the source of the lateral DMOSFET 30, and as a channel 51 of the lateral DMOSFET, which is opened and closed due to the voltage applied between the gate 68 and the source region 52. In alternate embodiments, the lateral DMOSFET has source and channel regions that are more distinct from one another rather than being encompassed within a single base region.
As shown, the drift region 54 of the RESURF superjunction lateral DMOSFET 30 is made up of alternating columns that alternate between columns 55 doped with Nxe2x88x92 impurities and columns 53 doped with Pxe2x88x92 impurities. Consequently, each respective column doped with Nxe2x88x92 impurities is depleted not only by RESURF region 50 (as in the RESURF lateral DMOSFET 20 discussed above) but also by the columns doped with Pxe2x88x92 impurities positioned on one or both sides of that column. Each respective column doped with Nxe2x88x92 impurities therefore receives proportionately greater depletion in the RESURF superjunction lateral DMOSFET 30 than an equivalent volume of the drift region of a RESURF lateral DMOSFET would receive. This extra depletion, for the reasons already discussed above with respect to the RESURF lateral DMOSFET 20, allows for the RESURF superjunction lateral DMOSFET 30 to maintain the same high breakdown voltage as the RESURF lateral DMOSFET despite having an even smaller drift region 54 between the drain 56 and the source region 52 (or a higher doping level).
The addition of the superjunction in the RESURF superjunction lateral DMOSFET 30 shown in FIG. 3 is highly advantageous in terms of the degree to which the specific on-resistance of the DMOSFET can be reduced relative to the RESURF lateral DMOSFET 20 without reducing the breakdown voltage of the DMOSFET. In certain embodiments, the specific on-resistance and size of the RESURF superjunction lateral DMOSFET 30 can be reduced by up to a factor of five relative to a comparable RESURF lateral DMOSFET 20 having the same breakdown voltage. Despite the reductions in the specific on-resistance enabled by the development of the RESURF superjunction lateral DMOSFET 30, however, further reductions in the specific on-resistance of lateral DMOSFETS are necessary as the sizes of logic and other components of integrated circuits continue to shrink and the appetite for including more and more components on a given integrated circuit continues unabated.
Further, despite the degree of reduction in specific on-resistance that the superjunction makes possible, the structure of the RESURF superjunction lateral DMOSFET 30 is limiting insofar as only half of the drift region 54 is made up of columns 55 doped with Nxe2x88x92 impurities. Because the RESURF superjunction lateral DMOSFET 30 is an NMOS device, the current passing between the drain 56 and the source region 52 when the RESURF superjunction lateral DMOSFET is in its on state is made up of electrons, and consequently only passes through that portion of the drift region 54 that is doped with Nxe2x88x92 impurities, namely, columns 55. Consequently, the overall conduction area of the drift region 54 for the RESURF superjunction lateral DMOSFET 30 is only approximately half that of a RESURF lateral DMOSFET 20 having a drift region 14 of the same overall size, and so the DMOSFET 30 in its on state has approximately twice the resistance and dissipates twice as much power (given the same current) as a RESURF lateral DMOSFET having a drift region of the same size.
It would be advantageous, therefore, if a new lateral DMOSFET could be developed that would further improve upon the RESURF superjunction lateral DMOSFET by allowing for a lateral DMOSFET with an even smaller specific on-resistance and consequently smaller overall size without any reduction in breakdown voltage. It would further be advantageous if an integrated circuit could be developed on which such a new lateral DMOSFET was employed, such that the integrated circuit could hold a greater number of components overall than was possible using conventional lateral DMOSFETs. It would additionally be advantageous if this new lateral DMOSFET overcame the limitations of the conventional RESURF superjunction lateral DMOSFET relating to the alternation of columns doped with Nxe2x88x92 and Pxe2x88x92 impurities within the drift region and relative increase in resistance due to the reduction in Nxe2x88x92 type material through which the DMOSFET conducts in its on state.
In accordance with one embodiment of the present invention, a MOSFET includes a source region, a first channel region proximate to the source region, a first gate electrode overlying the first channel region, a drain region, a second channel region proximate to the drain region, and a second gate electrode overlying the second channel region. A first channel is formed within the first channel region in dependence upon a first voltage applied to the first gate electrode with respect to at least a first portion of the source region, and a second channel is formed within the second channel region in dependence upon a second voltage applied to the second gate electrode with respect to at least a second portion of the drain region. The MOSFET further includes a drift region coupled between the first channel region and the second channel region, where the drift region is includes a set of alternating columns, each of which is also coupled between the first channel region and the second channel region. The set of alternating columns includes a plurality of columns doped with Nxe2x88x92 type impurities alternating with a plurality columns doped with Pxe2x88x92 type impurities.
In accordance with another embodiment of the present invention, a method of operating a MOSFET includes applying a positive voltage from a first gate electrode to a first channel region of the MOSFET, and conducting electrons from the source region to a drain region through a first plurality of columns doped with Nxe2x88x92 impurities within a drift region of the MOSFET in response to the application of the positive voltage. The method further includes applying a negative voltage from a second gate electrode to the drain region of the MOSFET, and conducting holes from the drain region to the source region through a second plurality of columns doped with Pxe2x88x92 impurities within the drift region in response to the application of the negative voltage.
The present invention further relates to an integrated circuit including a semiconductor transistor device. The integrated circuit comprises a means for conducting electrons in a first direction through the semiconductor transistor device in an on state, and a means for conducting holes in a second direction through the semiconductor transistor device in the on state. The integrated circuit additionally includes a means for controlling the conduction of electrons and holes by way of the application of at least one voltage. The means for conducting electrons depletes holes from the means for conducting holes and the means for conducting holes depletes electrons from the means for conducting electrons in an off state.
The present invention additionally relates to a method of operating a MOSFET. The method includes applying a positive voltage from a first gate region to a source region of the MOSFET, and conducting electrons from the source region to a drain region through a first plurality of columns doped with Nxe2x88x92 impurities within a drift region of the MOSFET in response to the application of the positive voltage. The method further includes applying a negative voltage from a second gate region to the drain region of the MOSFET, and conducting holes from the drain region to the source region through a second plurality of columns doped with Pxe2x88x92 impurities within the drift region in response to the application of the negative voltage.